A Split-Central-Buffered Load-Balancing Clos-Network Switch With In-Order Forwarding

Buffered Clos-network packet switch with per-output flow queues

Introduction: Current advances in chip fabrication allow high on-chip memory density. However, the pin count has mainly remained the same, thus limiting the number of ports a switch chip can support. A three-stage Clos-network switch [1] uses small switch modules, called input module (IM), central module (CM), and output module (OM), to implement a large switch (i.e. with a large number of port...

Three-Stage Clos-Network Switch Architecture with Buffered Center Stage for Multi-Class Traffic

Memory-space-memory (MSM) arrangement is a popular architecture to implement three-stage Clos-network switches with distributed arbitration. The scalability of this architecture, however, is limited by the round-trip communication delay between the first and the second stages. Moreover, virtual output queue (VOQ) does not completely remove the blocking in the buffered modules under multi-class ...

Packet Dispatching Schemes for Three-Stage Buffered Clos-Network Switches

Packet Loss Minimization in Load-Balancing Switch

Due to the overall growing demand on the network resources and tight restrictions on the power consumption, the requirements to the long-term scalability, cost and performance capabilities appear together with the deployment of novel switching architectures. The load-balancing switch proposed in [1,2] satisfies to the above requirements due to a simple distributed control and good performance c...

A Load-balancing Scheme for Parallel Internet Forwarding Systems

By investigating the flow level characteristics of Internet traffic, we are able to trace the root of load imbalance in hash-based load-splitting schemes. We show that workloads with Zipf-like distributions cannot be balanced using simple hashing. We have developed a novel packet scheduler that can achieve balanced load for parallel forwarding systems. Our scheduler capitalizes on the non-unifo...